1. Field of the Invention
The present invention generally relates to a semiconductor memory device employing GaAs MESFET's and, more specifically, to a static random access memory device employing normally-on type MESFET's as its transfer gates.
2. Description of Prior Art
An integrated circuit using a GaAs-MESFET (a gallium arsenide metal-semiconductor field effect transistor) collects the spotlight of attention, since it can operate at a high speed, as compared with the conventional integrated circuit using silicon. A high speed memory device using MESFET's such as, particularly, a buffer memory or a static RAM (random access memory) has been known very recently in this field. Among several circuit arranging methods of the static RAM, a six-transistor cell has been proposed as the most typical device, in which a flip-flop is constituted using a normally-off type MESFET as a driver FET and a normally-on type MESFET as a load. An example of this transistor cell is shown in FIG. 1. In this circuit diagram, FET's Q1 and Q2 are normally-off type MESFET's, and FET's Q3 and Q4 are normally-on type MESFET's, thereby constituting a flip-flop 10. Nodes 12 and 14 of flip-flop 10 are connected to bit lines BL.sub.1 and BL.sub.2 through a transfer gate made of normally-off type MESFET's Q.sub.5 and Q.sub.6. Gates of FET's Q.sub.5 and Q.sub.6 are connected to a word line WL. By arranging a plurality of such a memory cell 20 in a matrix form, a static RAM (not shown in detail) can be fabricated.
The reading and writing operations from and into memory cell 20 are executed by turning on FET's Q.sub.5 and Q.sub.6 by word line WL, by applying a signal voltage to flip-flop 10, and taking out the signal voltage of flip-flop 10 through bit lines BL.sub.1 and BL.sub.2.
In the circuit arrangement of memory cell 20, the time (access time) to read out information stored therein depends on the time required to charge and discharge stray capacitances of bit lines BL.sub.1 and BL.sub.2 through MESFET's Q.sub.5 and Q.sub.6. Therefore, it is well known that the greater the access time is reduced, the larger the current drivabilities of MESFET's Q.sub.5 and Q.sub.6 functioning as transfer gates becomes. However, in general, normally-off type MESFET's have their inherent drawbacks such that the parasitic resistance is large. The current drivability "I" is expressed by the following equation. EQU I=k(V.sub.th -V.sub.GS).sup.2
Where, k denotes a constant, V.sub.th is a threshold voltage of MESFET, and V.sub.GS is a gate-to-source voltage of MESFET. As will be obvious from this equation, the current drivability "I" is proportional to the square of the potential difference of .vertline.V.sub.th -V.sub.GS .vertline.. Therefore, in general, there are such inherent drawbacks that the current drivability "I" of the normally-off type FET is smaller than that of the normally-on type MESFET.
Since the normally-off type MESFET has such various inherent drawbacks as mentioned above, it tends to use the normally-on type MESFET for a memory device.
As shown in FIG. 2, therefore, the memory arrangement using normally-on type MESFET's Q.sub.7 and Q.sub.8 as transfer gates has been proposed. In this memory arrangement 30, the transfer gates of normally-on type FET's Q.sub.7 and Q.sub.8 are connected to the same flip-flop 10 as shown in FIG. 1. The current drivabilities of these transfer gates FET's Q.sub.7 and Q.sub.8 are larger and their own stray capacitances are smaller than those of the normally-off type FET's, so that the reduction of the access time can be realized.
However, there is a still problem in the above memory arrangement 30. That is, since each gate potential of MESFET's Q.sub.7 and Q.sub.8 needs to be negative with respect to the respective sources thereof in order to turn off normally-on type MESFET's Q.sub.7 and Q.sub.8, it is necessary to introduce a word line driver (not shown in detail) to render the potential of word line WL to be negative with respect to the potentials of nodes 12 and 14 in memory cell 30. Unless otherwise, the information already stored in the memory cell cannot be firmly held.
A level shift circuit is required in order not to obstruct the advantages of memory cell 30 using such normally-on type MESFET's as transfer gates. A buffered FET logic circuit is known as a typical example of the conventional level shift circuits. The typical buffered FET logic circuit is disclosed in, for example, "A GaAs 4k BIT STATIC RAM WITH NORMALLY-ON AND -OFF COMBINATION CIRCUIT", Technical Digest, 1984, GaAs IC Symposium, page 117, October 1984, Y. Ikawa et al. To use such a buffered FET logic circuit, two sets of positive and negative power sources V.sub.DD and V.sub.SS need to be used as a word line driver circuit.
However, the necessity of use of such two sets of positive and negative power sources will cause an unfavorable problem in terms of the arrangement of the memory system.
Therefore, in the semiconductor memory device using GaAs-MESFET's, there is a growing need for realizing such a memory device that a normally-on type GaAs-MESFET with a larger current drivability can be used as a transfer gate and at the same time, the high operating speed as a feature of this memory device is not harmed while being driven by a single power supply.
The present invention is made in consideration of the above-mentioned technical trade off aspects, and it is therefore an object of the invention to provide a semiconductor memory device employing GaAs-MESFET's. In spite of the fact that normally-on type MESFET's are used as transfer gates, this memory device can be driven under a single power supply and is operable at a high speed.